The present invention relates to an integrated clock generator, particularly for driving a semiconductor memory with a test signal.
Dynamic random access memory (DRAM) chips with high and increasingly great storage densities are tested using cost-intensive memory test systems. In this context, the testers use test programs to check the operability of the memory chips. This involves applying signals with precisely defined voltage levels to the semiconductor circuit to be tested at exactly defined times. While a read function of a device under test (DUT) is being checked, it is furthermore possible to read signals coming from the DUT into the test unit at precisely defined times and to compare them with expected signal values. The specifications of DRAMs manufactured today already require degrees of timing precision down to a few tens of picoseconds for test purposes; for example xe2x80x9caddress setup timingxe2x80x9d of 200 picoseconds requires that address data be tested for availability exactly 200 picoseconds before the rising edge of a clock signal.
Since the memory tests described which have the high demands on precision which have been described, already result in high production and test costs today, it is desirable for the test costs to be reduced by virtue of function tests on the memory chips, particularly high-frequency tests, allowing testing first at an early time in the value-adding chain and second without the need for cost-intensive test equipment, as a result of the incorporation of self-test facilities on the memory chip itself.
It is accordingly an object of the invention to provide a integrated clock generator, particularly for driving a semiconductor memory with a test signal that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which is inexpensive to produce and at the same time satisfies the described high demands on the timing precision of the signals produced.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated clock generator. The clock generator contains an input/output interface for inputting or outputting data to or from the integrated clock generator, a clock source outputting a reference signal, and a delay locked loop having a first input coupled to the input/output interface for receiving an input signal from the input/output interface. The delay locked loop has a second input coupled to the clock source and receiving the reference signal. The delay locked loop has an output providing an output clock signal based on the input signal and the reference signal and is coupled to the input/output interface. A selection circuit is coupled to the delay locked loop for changing over from a first, synchronizing mode of operation to a second, freewheeling mode of operation. An adder/subtractor is coupled to the delay locked loop for providing a settable delay between the input signal and the reference signal in the second, freewheeling mode of operation.
The integrated circuit having the delay locked loop is based on the principle that, initially, in the first mode of operation, the input signal is synchronized with the reference clock signal, and then, in the second mode of operation, during which the feedback for the delay locked loop is removed, the adder can be used to produce a desired delay between the input signal and the reference signal. This affords a simple way of providing the desired, exact timing for implementing a built-in self-test (BIST) on semiconductor memory chips.
During the first mode of operation, synchronization can be effected, by way of example, by virtue of the adder adding a delay of 0, which thus permits precise synchronization between the input signal and the reference signal.
In the first mode of operation, the delay locked loop described corresponds to a conventional delay locked loop (DLL).
Since the principle described allows a highly precise delay for a data signal with respect to a reference clock signal, the integrated circuit described can be used, in particular, for driving semiconductor memories, for example DRAMs, whose test specifications demand degrees of precision in the picosecond range.
By way of example, the integrated circuit described can be used to generate a test data signal precisely 200 ps before the rising edge of the reference clock.
The integrated circuit can be integrated in a semiconductor memory chip and is accordingly suitable for providing a BIST.
Since the test signal mode, namely the second mode of operation, is normally required only for short periods of time during a BIST, no problems arising from possible temperature drifts are to be expected for the described simple configuration of the circuit with an open-loop mode for the delay locked loop.
The principle described allows a significant reduction in the considerable test costs for DRAMs, and hence a reduction in the production costs for DRAMs as a whole.
The simple manner in which the principle described can be implemented results in that it can be applied inexpensively, for example in mass production.
In one preferred development of the invention, an adder/subtractor included by the delay locked loop is coupled to the selection circuit for the purpose of blocking upward and downward counting during the second mode of operation.
To compare an input signal with a reference signal, a delay locked loop normally has a comparator having a downstream adder/subtractor that is driven on the basis of the signal difference between the two input signals on the comparator. To remove the synchronization during the second mode of operation by interrupting the feedback for the delay locked loop, it is easy to effect the interruption in the present integrated circuit by virtue of the upward and downward counting being blocked during the second mode of operation. Therefore, no further regulation by the delay locked loop is possible. The latter is therefore in an open-loop mode, which results in that a programmable and hence highly precise delay can be set between the input signal and the clock signal, which had been synchronized to one another beforehand.
Since the up/down counter described is normally present in delay locked loops anyway, it is possible to change over between the first mode of operation and the second mode of operation with particularly little complexity.
In another preferred embodiment of the invention, the delay locked loop contains a delay module whose input side is coupled to the clock source for the purpose of transmitting the reference signal and whose output side provides signals which have graduated delays and are derived from the reference signal. The delay locked loop also contains a multiplexer having a control input that is connected to an output of the adder/subtractor.
Such a delay device, known as a xe2x80x9cdelay linexe2x80x9d, provides a number n of signals which are derived from the clock signal and each have a graduated delay, differing from that of the others, with respect to the reference clock signal. The multiplexer is driven by the adder/subtractor and selects one of the delay lines of the delay module according to the difference between the input signal and the reference clock signal. In this case, the multiplexer is in the form of a (1-of-n) multiplexer.
Such a delay module with a downstream multiplexer allows particularly fast locking of the delay locked loop with a particularly simple configuration.
In addition, the adder already described can easily be coupled to the delay module and to the multiplexer for the purpose of providing a settable delay in the second mode of operation.
In another, preferred embodiment of the present invention, the input/output interface contains an output driver whose output side is coupled to the first input of the delay locked loop and whose input side is coupled to the output of the delay locked loop.
Such an output driver in an integrated circuit is known as an xe2x80x9coff-chip driverxe2x80x9d (OCD). Such output drivers are normally used for driving data, for example test data, from a semiconductor memory chip to the outside, that is to say into a unit connected to the chip, via an I/O pad connected to the output of the output drivers. On the basis of the preferred embodiment, the output driver is connected into the feedback chain of the delay locked loop, which results in that the highly precise test signals which can be produced with the described configuration are available directly on the input/output interface of a semiconductor memory.
The particular feature in this case is that the off-chip driver OCD normally present anyway can also be used for providing test signals, and hence the highly precise test signals provided can be supplied to an integrated semiconductor memory as far outside as possible, namely on its I/O pad, which allows as many parts of the semiconductor memory as possible to be tested very realistically.
In another, preferred embodiment of the present invention, the input of the output driver has a multiplexer connected to it which has a first input, to which a data signal can be supplied, and which has a second input, which is coupled to the output of the delay locked loop.
Despite the joint use of the OCD by the delay locked loop, the multiplexer described can also be used to allow conventional use of the input/output interface of the integrated circuit, since it is normally possible for data signals needing to be driven from the integrated circuit to the outside to be provided on an I/O pad of the input/output interface by the output driver as a result of changing over using the multiplexer.
In another, preferred embodiment of the present invention, to couple the first input and the output of the delay locked loop, a bit pattern generator is provided whose output provides a bit pattern having the frequency of the output clock signal.
The bit pattern which can be provided is preferably a periodic bit pattern, for example an alternating sequence of logic ones and zeros.
Accordingly, the bit pattern generator makes it possible to provide the input signal from the output clock signal of the delay locked loop.
In another, preferred embodiment of the present invention, the input/output interface contains an input driver for driving a semiconductor memory.
In this case, the input of the input driver is connected directly to the output of the output driver and at the same time can be activated thereby, so that the highly precise test signals which can be produced with the integrated circuit can be supplied directly on a connection on the semiconductor memory which is as far outside as possible, and hence the quality of the BIST provided by the principle described is just as high as if the test signals were supplied on the I/O pad of the semiconductor memory, that is to say having been produced outside the semiconductor memory chip.
In another, preferred embodiment of the present invention, the clock source is provided in the form of an external source, that is to say is formed outside the integrated circuit and outside the semiconductor memory chip, and is connected to the integrated circuit via a clock pad. The clock source can be used, by way of example, to provide a reference signal having a clock frequency of 400 MHz.
In an alternative, preferred embodiment of the present invention, the clock source is formed internally in the integrated circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a integrated clock generator, particularly for driving a semiconductor memory with a test signal, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.